1. Field of the Invention
The present invention relates to serial communications, and, more particularly, to a method and apparatus for effecting synchronous pulse generation for use in variable speed serial communications.
2. Description of the Related Art
A Universal Serial Bus (hereinafter referred to as “USB”) permits a variety of peripheral devices, such as a printer or scanner, to be connected to a generic port in a host computer. During communication between a host computer and peripheral device via a USB, data is transmitted over the bus, but the USB does not transmit a clock for synchronization. Therefore, it is necessary for a USB receiver to have some mechanism to synchronize itself with the incoming data. The USB Specification (version 1.1) describes methods of encoding transmitted data for keeping a receiving device synchronized with the incoming data. Each packet transmitted on USB begins with a synchronization field to allow the receiver to synchronize with the transmitted data. The receiver is kept in synchronization with the transmitter by the non return to zero invert (hereinafter referred to as “NRZI”) encoding and by bitstuffing if the NRZI encoding does not signal a transition after 6 bits.
Current USB systems utilize multiple clocks, one of which is a 12 MHz clock that is synchronized to the data on the USB. For example, U.S. Pat. No. 5,910,742 issued to Snyder, et al. (hereinafter referred to as “Snyder”) discloses a circuit and method for synchronizing a data signal to one of a plurality of clocks. Snyder discloses using two pulses generated by the transmission of data to select one of many clocks to use for recovering the transmitted data. In Snyder, a clock generator is configured to generate a plurality of clocks and/or a logic circuit is configured to select the clock signal having the closest timing in relationship with the data signal.
Typically, USB systems include a USB controller for synchronizing the timing relationships by relying on feedback to synchronize incoming data. A USB controller in a typical system uses a digital phase-locked loop (hereinafter referred to as “DPLL”) circuit that runs on a 48 MHz clock. The USB data signals, commonly referred to as D+ and D−, are inputs into the DPLL and the DPLL outputs a 12 MHz clock signal synchronized to the USB data. The USB controller uses the DPLL clock signal to extract the bit values of the USB data. In many systems, the clock synchronized with the USB is unsuitable for other logic that interfaces with the USB because the clock rate is slower and the clock frequency or period varies. For example, the 48 MHz clock signal may be divided to generate a 24 MHz clock signal for a processor or other logic. Thus, a separate clock is used for the processor and the other logic in those systems. Multiple clocks require additional logic for synchronization between the clock domains and multiple clocks complicate the testing of the system logic.
One method and apparatus for synchronizing circuitry between multiple clock timing domains, such as a USB, is disclosed in U.S. Pat. No. 5,923,193 issued to Bloch, et al. (hereinafter referred to as “Bloch”). In FIG. 2 of Bloch, a timing diagram illustrates a source clock, a fixed clock and a latch signal. Bloch discloses that the source clock signal has a 48 MHz frequency and that the clock divider circuit divides the source clock signal frequency to produce a 12 MHz clock signal. It is important to note that Bloch discloses passing the arriving data signal through a DPLL, and thus, Bloch discloses at least two clock domains, the system clock and the DPLL clock. Once created, these two clock domains are delayed in such a way that they are staggered slightly aiding in decoding the incoming data. A latching pulse, created using the internal 48 MHz clock, pulses every four edges of the 48 MHz clock. These signals along with a latching scheme are used to decode the incoming data.
Attempts have been made to optimize the flow of isochronous data and clock rate information over a USB, such as that disclosed in U.S. Pat. No. 5,958,027 issued to Gulick (hereinafter referred to as “Gulick”). In Gulick, the USB conveys a control signal to a data producer to increase or decrease the clock rate of the data producer based upon the level of data within the buffer of the USB. Thus, in Gulick the clock rate of the data producer or data transmitter is changed.
The IEEE 1394-1995, IEEE-1394a and IEEE-1394b standards define buses which allow high speed transfers of data to and from a variety of peripheral devices such as a printer, scanner, digital video equipment and high-performance mass storage.
The 1394a bus uses two twisted pairs, TpA and TpB, to transfer data between devices. Signals on the 1394a bus twisted pairs are also referred to as Data and Strobe. During communication between, for example, a host computer and a peripheral device via a 1394a bus, data is transmitted without a clock signal for synchronization. Therefore, it is necessary for a device receiving data via a 1394a bus to have a mechanism to synchronize the data for use therein. Whereas the Strobe signal only transitions when the generating clock transitions and the Data has not changed, the generating clock of Data and Strobe can be recovered by directing the Data and Strobe signals through an exclusive-OR gate. This recovered clock can then be used to sample the incoming Data. An S-notation is used relative to the 1394a bus to indicate the approximate bus speed in Mbits per second. For example, S400 is 393.216 Mb/s or nearly 400 Mb/s. The IEEE 1394-1995 and 1394a standards allow for data rates up to S400. To allow faster data rates, changes had to be made to the method of sending and recovering data to and from each device. These changes are made in the 1394b revision, which allows for data rates of up to S3200.
To enable the IEEE-1394b bus to have higher aggregated throughput, dual simplex communications are used, hence each TpA and TpB pair transmits continuously in one direction, thus allowing a device to receive data while simultaneously transmitting data. The IEEE-1394b bus, while allowing for faster data rates, eliminates the Strobe signal and hence the clock recovery outlined above for the 1394a bus. To prepare parallel data to be transmitted over the IEEE-1394b bus, the data is first scrambled to reduce radiated emissions. The scrambled data is then encoded using an 8B/10B encoding technique which creates 10 bits for each 8 bit word so as to ensure DC balance and allow clock recovery. Clock recovery is possible since the 8B/10B encoding guarantees that a transition will occur at least once every 5 bits. The transmitter device then serializes the scrambled, encoded data for transmission on the IEEE-1394b bus.
At a receiving device the serial data is received and by use of a phase-locked loop circuit, which monitors transitions in the data to stay locked to the bus frequency, the data is recovered by sampling the serial data. The data is then processed into 10 bit parallel data which is decoded using an 8B/10B decoder into 8 bit words which are then unscrambled into the recovered parallel data which was sent from the sending device.
What is needed in the art is a method and apparatus for effecting synchronous pulse generation for variable speed serial communications using a simplified hardware configuration.